In recent years, as miniaturization of the semiconductor process has advanced, designing an SRAM that has a small area and which operates on a low operation voltage is progressing. As a result, the stability of a memory cell is reduced. In order to solve this problem, the stability at the time of write is secured by boosting the potential of a bit line of a bit line pair, whose potential is to be reduced, to a negative (minus) potential at the time of the write operation.
A write driver is generally formed by an inverter connected between a high potential power source line and a reference potential power source line. In order to boost the bit line to a negative potential, the reference potential power source line of the inverter forming the write driver is set as an independent low-side drive line, the low-side drive line is temporarily set to a negative potential at the time of the write operation, and in other cases, the low-side drive line is set to the same potential as that of the reference potential power source line.
In order to enable the above operation, a capacitive element and a boost control transistor are provided. One terminal of the capacitive element is connected to the low-side drive line. A boost signal is applied to the other terminal of the capacitive element. The boost control transistor is connected between the low-side drive line and the reference potential power source line. The boost signal is applied to a gate of the boost control transistor. At the normal time, the boost signal is at the high level and the boost control transistor turns on, the potential of the low-side drive line becomes a potential VSS of the reference potential power source line, and the capacitive element is charged to the potential difference between the potential of the boost signal and the VSS. At the time of the write operation, if the boost signal changes to the low level, the boost control transistor turns off and the potential of the low-side drive line changes to a negative potential by the charges charged in the capacitive element. The low-side drive line is connected to a bit line, which is driven to the low side, of a plurality of bit line pairs (column) via a transistor, etc. forming an inverter of the write driver, and the bit line which is driven to the low side is driven to a negative potential.
In the SRAM circuit as described above, the potential difference caused by the boosting differs depending on the variations in the operation voltage, the process conditions, etc. For example, in the case where the operation voltage of the boost signal is high, the low-side drive line changes to a large negative potential. In response to this, if the potential of the bit line of the selected bit line pair, which is driven to the low side, also changes to a large negative potential, there occurs a case where the threshold voltage of a transfer transistor of a non-selected memory cell is exceeded, and therefore, there has been a problem that data is written erroneously to the non-selected memory cell. Further, if the low-side drive line changes to a large negative potential, the voltage that is applied to the transistor of a non-selected column switch becomes higher than the threshold voltage, and therefore, the transistor of the non-selected column switch turns on, and a result there has been a problem that data is written erroneously to the non-selected cell.
In order to solve the problem of an over-boost as described above, Patent Document 1 has disclosed a clamp circuit that clamps the potential of the low-side drive line.
Further, Patent Document 2 has disclosed a configuration for controlling a potential difference that is boosted by using a variable capacitor as a capacitive element.